The Short Course will be take place on Sunday, September 28, 2003 from 8 :00 am to 5 :15 pm. It will be divided into three 2-hours courses given by three experts from the industry and the university. This year, the short course program will address both technology, design and reliability issues.

This year, the short course will be recorded on a DVD that will be available on the last day of the conference. This will be the opportunity to bring your virtual short course at home or at your office and to directly play it on your own computer. Reserve your DVD upon your short course registration.

High Speed SiGe HBT Device Design and Fabrication

SiGe:C HBT Device Technology: What is the Big Deal?

Instructor : Dr. Peter Magnee, Philips Research , Leuven (NETHERLANDS)

SiGe and SiGe:C heterojunction bipolar transistors (HBTs) are rapidly finding their way into radio-frequency (RF) BiCMOS technologies. Hence, a good understanding of the device behavior and fabrication process is of key importance. In this short-course, a brief tutorial is given on the device operation of Si/SiGe HBTs: why do we put SiGe in the base? Also, the effect(s) of incorporating of small amounts of C will be discussed.

SiGe and SiGe:C devices are fabricated by means of epitaxial growth. Different aspect of the various growth techniques will be reviewed, with the main focus on reduced-pressure chemical vapour deposition (RPCVD); selective growth versus non-selective growth, growth conditions versus C-incorporation, etc.

Finally, the way the HBT is integrated in a full, bipolar or BiCMOS, process has a significant impact on the device parasitics and hence, on the RF performance. An overview will be given on the different integration schemes that can be found in the literature, each with their own advantages and disadvantages.

Peter H.C. Magnee was born in Vlissingen, The Netherlands in 1969. He received his M.Sc. and Ph.D. degree in applied physics from the University of Groningen (The Netherlands) in 1991 and 1996 respectively. In 1996 he joined Philips Research in Eindhoven, where he worked in Si-based bipolar transistors for wide-band and RF-power applications.
In 2000 he moved, together with the Silicon Processing Technology Sector, to Philips Research Leuven. Since 2000 he is the project leader of the Advanced Bipolar/BiCMOS Technology project, which focuses on different technology- and device-options based on Si/SiGe heterojunction bipolar transistors. Dr. Magnee is a member of the Process Technology subcommittee of the BCTM.

Si/SiGe HBT MMIC design techniques for 20 GHz and beyond

Instructor : Prof. Hermann Schumacher, University of Ulm (GERMANY)

Content :

This course addresses the commercial relevance of silicon-based ICs and technologies for applications at 20 GHz and above. The requirements placed on SiGe HBT‚s for circuit design and operation at millimeter-wave frequencies is first examined. Passive devices and structures are critical to successful circuit implementations at these frequencies, and therefore the passive structures needed for micro and millimeter-wave IC implementations on a silicon substrate are discussed in detail. Important aspects of the design of monolithic microwave integrated circuits (MMIC‚s), including circuit topologies, physical layout, and substrate effects are then described. Circuits developed for operation at 24GHz and above will be used as design examples. Finally, a look ahead at how deep into the millimeter-wave range we may be able to reach in future is projected.

Hermann Schumacher was born in Siegen, Germany in 1957. He graduated with the Diplom- and Doktor-Ingenieur degrees from RWTH Aachen in 1982 and 1986, respectively. In 1986, he joined Bellcore (now Telcordia) in Red Bank, NJ as a Member of the Technical Staff, working on InP-based planar photodetectors and heterojunction bipolar transistors.
In 1990, he became a professor at the University of Ulm, Germany. Since then, his group has been working predominantly on Si/SiGe heterostructure devices and circuits, with special emphasis on receiver circuits and low-cost microwave ICs. He is the director of the Competence Center on Integrated Circuits in Communications at the University of Ulm (founded in 2001) and of the International Master Program on Communications Technology (established in 1998). Currently, he also serves as Vice President, Research, for the University of Ulm.

All About On-Chip ESD Protection Design: Mixed-Mode Simulation And ESD For RF/Mixed-Signal ICs

Instructor : Prof. Albert Wang, Illinois Institute of Technology (USA)

Abstract : ESD (Electro-Static Discharge) induced failure becomes a major IC reliability problem as IC technologies migrate into the VDSM ULSI regime. On-chip ESD protection circuitry is required to protect IC chips against ESD damages. Particularly, ESD protection design for mixed-signal & RF ICs emerges as a new challenge to IC designers. Unfortunately, trial-and-error approaches still dominate the current ESD design practices. This lecture intends to discuss all key aspects of practical ESD protection designs. It will cover the principles of ESD protection design, a new mixed-mode ESD simulation-design methodology developed at the Integrated Electronics Laboratory, Illinois Institute of Technology, and the unique problems for RF/mixed-signal ESD protection. Practical ESD protection circuit design examples will be provided. This lecture aims to assist IC designers in dealing with real-world ESD protection circuitry design problems.

Albert Wang received the BSEE degree from Tsinghua University, China, in 1985 and the PhDEE degree from The State University of New York at Buffalo in 1995. He was with National Semiconductor Corporation until 1998 when he joined the Faculty of Electrical and Computer Engineering of the Illinois Institute of Technology, where he is currently directing the Integrated Electronics Laboratory. His research interests center on analog/mixed-signal/RF ICs, advanced on-chip ESD protection, IC CAD and modeling, SoCs and semiconductor devices, etc. He received the CAREER Award from the National Science Foundation in 2002 and the Sigma Xi Award for Excellence in University Research from IIT in 2003. He is the author of the book On-Chip ESD Protection for Integrated Circuits(Kluwer,2002, ISBN: 0-7923-7647-1) and more than sixty papers in the field, and holds several U.S. patents. He is an Editor for the IEEE Electron Device Letters and an Associate Editor for the IEEE Transactions on Circuits and Systems II. He is an IEEE Distinguished Lecturer for the Electron Devices Society and the Solid-State Circuits Society, an IEEE EDS AdCom Member, Vice Chair of EDS Regions and Chapters Committee for North America West and a Member of the EDS VLSI Technology and Circuits Committee. He serves as TPC Member, Sub-Committee Chair and Session Chair for many conferences, e.g., IEEE CICC, RFIC, APC-CAS, ASP-DAC, etc. He is an IEEE Senior Member, a frequent speaker at various industrial/academic/international forums and a frequent consultant to the IC industry.