Nanocomputing and related enabling technologies hold the promise of higher performance and lower power consumption, as well as increased communication capability and functionality. In addition to the impact on today computerized systems, such a trend is an essential lever to foster the emerging cyberphysical system paradigm. However, the dependability and security of these unprecedentedly small devices, of their deployment, and of their interconnection remains uncertain. The main sources of concern are:

• Nanometer devices are expected to be highly sensitive to process variations. The guard-bands used today for avoiding the impact of such variations will not represent a feasible solution in the future. As a consequence, timing errors and their higher frequency of occurrence have to be addressed.
• New and intricate failure modes, specific to nanoscale dimensions and new materials, are expected to raise serious challenges to the design and test engineers.
• Environment induced errors, such as single event upsets (SEU) or single event transients (SET), are likely to occur more frequently than in the case of conventional semiconductor devices.
• Design of hardware architectures encompassing resilience techniques are needed to achieve the development of reliable and highly energy efficient systems.
• The increased complexity of the systems based on nanotechnology will require improved computer aided design (CAD) tools, as well as better validation techniques.
• The security of nanocomputing systems may be threatened by malicious attacks targeting new vulnerable areas in the hardware.

Hardware implemented fault tolerance features (encompassing error correcting codes, as well as space and time redundancy) will be increasingly employed for dealing with these dependability issues. Providing high dependability to the end users will require improved error reporting, recovery, and system manageability. As a consequence the role of software solutions will increase as well. Software will also play the leading role in the improvement of design and validation tools. Furthermore, improved parallel processing programming paradigms are needed due to the advent of multicore processor and Network-on-Chip architectures.

Scope and Topics

The previous four editions of the Workshop — held from DSN-2007 to DSN-2010 — have increasingly attracted the attention of the DSN audience to the importance of hardware-related issues. Indeed, DSN is the appropriate forum for discussing these challenges and potential solutions.

Accordingly, building on the success of these previous editions, we would like to continue to focus the Workshop on Designing, Manufacturing, and Assessing Dependable Nanocomputing Systems, with a special attention being paid, for this year's edition, to the following topical areas:

• Nanocomputing architectures for high dependability and energy-efficiency
• Design, validation, and manufacturing techniques for coping with increased complexity
• Dependability of application-specific nanocomputing architectures, including SoCs-NoCs
• Failure modes and testing issues specific to nanocomputers

Contributions related to these main topics will allow the Workshop to continue the debate on the increasingly developing issues posed by nanocomputing, as well as the best solutions for providing highly dependable and secure systems and networks to the end-users. In that respect, potential topics of interest include, but are not limited to: failure modes and risk assessment, yield and mitigation techniques in nanoscale technologies, vulnerability analysis of hardware devices and design of countermeasures for secure operation, on-line adaptive and reconfigurable nanoarchitectures, design techniques for developing resilient nanosystems, fault-tolerant architectures specific to nanoscale circuits, scalable verification and testing methodologies, network on chip and communication protocols, etc.